Byte Mode

With later implementations of the parallel port interface, some manufacturers, led by IBM on the PS/2 parallel port, added the capability to disable the drivers used for driving the data lines, and allowed the data port to become an input read data port. This enables a peripheral to send an entire byte of data to the PC in one data transfer cycle by using the 8 data lines, rather than the two cycles required using the Nibble mode.

This ability enables a Byte mode for reverse channel data transfer that can be used to provide data rates into the PC approaching that of the Compatibility mode, from the PC. This type of port is sometimes referred to as a "enhanced bi-directional" port, and has caused some confusion when mistaken for an Enhanced Parallel Port (EPP).

The following table identifies the Byte mode signal names, and figure 3 shows the handshake for a Byte mode data transfer.

Table 1 -- Byte Mode Signals

Figure 1 -- Byte Mode Data Transfer Cycle

Byte Mode signal transitions:

1. Host signals ability to take data by asserting HostBusy low

2. Peripheral responds by placing first byte on data lines

3. Peripheral signals valid byte by asserting PtrClk low

4. Host sets HostBusy high to indicate that it has received the and is not yet ready for another byte

5. Peripheral sets PtrClk high to acknowledge host. Host pulses HostClk as an acknowledgement to the peripheral

6. States 1 through 5 repeat for additional bytes