Availability: Immediate
Price: $90,000
To Order/More Info: 858-576-4354

Peripheral Interface Controller "Core" Now Available In Multiple Formats

SAN DIEGO, March 20, 2000 -- Warp Nine Engineering announced today availability of a Verilog model for its IEEE 1284 Peripheral Interface Controller (PIC) chip, in addition to the previously available VHDL model of the W91284PIC.

The model enables OEMs to add industry-standard IEEE 1284-compliant functionality to their high volume peripheral products.  The OEM can integrate the model into their ASIC as is, or modify it to meet their particular application needs.  The Verilog model includes a full Test Bench to enable easy verification and testing.  The IEEE 1284 standard provides a high-speed, bi-directional means of allowing multiple peripheral use through the parallel port of a host personal computer.

The one-time, single-use license fee of $90,000 is an economical way to include the Warp Nine Engineering's IEEE 1284 PIC technology in very high production-run scenarios.  OEMs can now buy the single-use rights to the source code for unlimited production runs.  For manufacturers with smaller production requirements, they may purchase purchasing the W91284PIC chips at under $5 per unit in quantity. 

The Verilog model is best suited for higher-end peripherals, such as scanners, specialized printers, graphic Raster Image Processing equipment, Digital Subscriber Loop modems, satellite television receivers and "set top box" interfaces.  This model can be used in any application that requires a drop-in parallel port interface.

In addition to the ability to simply transfer code, Warp Nine Engineering's support of Verilog allows OEMs to more easily test and integrate IEEE 1284 capabilities with other "blocks," or codes enabling additional capabilities planned for the finished product. 

Warp Nine Engineering's Solution Emphasizes Easy Implementation

Warp Nine Engineering's IEEE 1284 PIC solution emphasizes easy implementation for the OEM and thus incorporates all of the IEEE protocols, including Device_ID for plug and play.  The source code provides hardware support for the various communication modes defined by the IEEE standard, such as Nibble, Byte, ECP and EPP.  Dual FIFOs are implemented to support burst rate matching between the host and the peripheral.  The host interface to the peripheral is based on a simple microprocessor interface, so the OEM does not need to know anything about the parallel port in order to achieve maximum performance, compliant parallel port connectivity.

The Verilog HDL (Hardware Description Language) enables programmers to write a textual format for describing electronic circuits and systems.  Initially designed as a proprietary hardware modeling language, Verilog has evolved into a versatile HDL enabling designers to write system-specific codes for a variety of uses such as system simulation, timing and test analysis, fault grading and logic synthesis.  Verilog is also used to design application-specific integrated circuits (ASICs), a non-specific set of logic gates assimilated on a chip, whose functions are later defined by translating the Verilog code, also known as the synthesis process.

Available immediately, the source code for Warp Nine Engineering's W91284PIC is available in the Verilog HDL for a one-time, single-use license fee of $90,000.  The VHDL model, which includes test vectors but no Test Bench, is available for $75,000.  For more information, contact the company at 858-576-4354, or visit the web site at www.fapo.com. 

Warp Nine Engineering

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